Power/energy consumption has increased significantly with every chip generation. With the reduced transistor sizes in modern processors, the per area power density is approaching that of a nuclear reactor. Consequently, power reduction has become a design goal, with power saving features widely recognized as representing the next phase in the advancement of microprocessors. Portability and reliability requirements of emerging applications further underline this trend.
Major processor vendors realize that they must compete in terms of the power consumption of their chips as well as chip speed. Typical approaches to reduce power consumption (e.g., by reducing supply voltage and/or clock rate) negatively impact performance. Other approaches do not scale between design generations (e.g., as clock rates increase, due to changed critical paths, the value of many circuit or microarchitecture based energy reduction approaches is reduced).
The challenge is to reduce the energy consumed in processors without sacrificing performance, and with solutions that scale between processor generations. With increased. Internet usage and growing desire for wireless communications, the processor market is being driven to produce smaller and more powerful chips that do not drain significant amounts of power.